このディレクトリの索引

#  module regwrite
#    (
#    output reg rout,
#    input clk,
#    input [3:0] in,
#    input [3:0] ctrl
#    );
#    always @(posedge clk)
#      case(1)
#        ctrl[0]:rout <= in[0];
#        ctrl[1]:rout <= in[1];
#        ctrl[2]:rout <= in[2];
#        ctrl[3]:rout <= in[3];
#      endcase // case(1)
#  endmodule // regwrite
#  module regwrite

regwrite(_rout,_clk,_in,_ctrl) :-
        case(_ctrl,_rout).

case(_ctrl,_in,_rout) :-
        nth0(0,_ctrl,1),
        nth0(0,_in,_rout).
case(_ctrl,_in,_rout) :-
        nth0(1,_ctrl,1),
        nth0(1,_in,_rout).
case(_ctrl,_in,_rout) :-
        nth0(2,_ctrl,1),
        nth0(2,_in,_rout).
case(_ctrl,_in,_rout) :-
        nth0(3,_ctrl,1),
        nth0(3,_in,_rout).